The invention relates to a circuit for converting logic levels between logic of the type utilizing pairs of emitter-coupled transistors (ECL, CML) and logic of the transistor-transistor type (TTL), comprising a differential input stage which includes at least one first transistor and one second transistor whose emitters are coupled, and a principal current source which is connected between said coupled emitters, and a negative supply voltage source, their collectors being connected to a positive supply voltage source via a first resistor and a second resistor, respectively, the base of the first transistor being connected to a reference voltage whilst that of the second transistor receives an input signal whose level is to be translated, a first diode and a second diode whose anodes are connected to ground and whose cathodes are connected to the collector of the first transistor and the second transistor, respectively, and also comprising an output stage which includes a fifth transistor and a sixth transistor whose collector-emitter paths are connected in series, the emitter of the fifth transistor being connected to ground, its base being connected to the collector of the first transistor and its collector being connected to the emitter of the sixth transistor at a point which forms the output of the converter circuit, the base of the sixth transistor being connected to the collector of the second transistor whilst its collector is connected to the positive supply voltage source.
A converter circuit of this type has already been produced in cells which are marketed under the name ACE, but this circuit has the drawback that it has only two low-impedance states.
However, there is an increasing need for circuits of this kind which can be arranged with their outputs connected in parallel. For such an application it must be possible to set the circuits to a third state in which their output presents a very high impedance, independently of the signals received on their inputs. The parallel-connected circuits are thus used by setting n-1 circuits to the third state, the output of a selected circuit being in the first state or the second state in dependence of the signal received on its logic input.